Nowadays, in the rapid development of semiconductor storage device, DRAM, EEPROM, FLASH and other advanced storage devices have been widely used in computers and mobile communication terminals, attributed to their advantages such as high density, low power consumption and low price. Due to the requirements of low power consumption and low cost, a power supply of the storage device always has a low voltage, such as 2.5V, 1.8V, etc. However, in order to implement “write”, “erase” and other operations of information, a programming voltage and an erase voltage which are much higher than the power supply voltage are always required, such as 8V, 12V, etc. Therefore, a charge pump circuit is widely used in the storage device. The charge pump circuit is used to obtain higher operation voltages for the storage device from the lower power supply voltage, such as the programming voltage, the erase voltage, etc.
If the higher operation voltage is established and applied to the storage device too fast, the storage device may be damaged and reliability of the storage device may be reduced. In order to prevent the above situation, an establishment speed of the operation voltage should be controlled. Hence, in the conventional Flash, a control circuit is always configured to control boost speed of the operation voltage.
A structure diagram of a conventional circuit for controlling erase voltage of Flash is illustrated in FIG. 1. The circuit includes:
a charge pump 11 adapted for output a high voltage HVE;
a mirroring constant current source 12 which includes a first PMOS transistor P1, a second PMOS transistor P2, a switch K and a current source Ibias, where a drain of the first PMOS transistor P1, a gate of the first PMOS transistor P1, a gate of the second PMOS transistor P2 and a first terminal of the switch K are connected together, a second terminal of the switch K is connected with a first terminal of the current source Ibias, and a second terminal of the current source Ibias is connected with ground;
a capacitor, where a first terminal of the capacitor is connected with ground; and
an NMOS transistor N, where a source of the NMOS transistor, a source of the first PMOS transistor P1, a source of the second PMOS transistor P2 and an output terminal of the charge pump 11 are connected together, a gate of the second NMOS transistor N2, a drain of the second PMOS transistor P2 and a second terminal of the capacitor C are connected together, and a drain of the NMOS transistor N is adapted for outputting an erase voltage VEP.
FIG. 2 illustrates a boost process of the erase voltage in FIG. 1. As shown in FIG. 2, the high voltage HVE is quickly generated and established by the charge pump 11; when the switch K is closed, the NMOS transistor N is turned on, and the capacitor C is charged; a drain voltage Gramp of the second PMOS transistor P2 is boosted continuously, and the erase voltage VEP is also boosted along with the drain voltage Gramp. Thus, the erase voltage VEP can be slowly established by controlling the boost speed of the drain voltage Gramp.
It can be seen from the circuit shown FIG. 1 that, VEP=Gramp−Vth1 and Gramp=HVE−Vth2, where Vth1 is the threshold voltage of the NMOS transistor N, and Vth2 is the threshold voltage of the second PMOS transistor P2.
However, the above circuit has the following disadvantages:
1) the charge pump 11 needs to generate a voltage HVE which is higher than the erase voltage VEP, so that the power consumption of the circuit is increased, and performance requirements of electric devices in the circuit are also increased;
2) in the working process (for example, after a plurality of erase operations are performed), threshold voltage Vth1 of the NMOS transistor N may be changed, so that the erase voltage VEP may deviate from a target value, and the performance of the device are affected.